C8051F93X Datasheet, PDF (252/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
22.5. SMBus Transfer Modes
The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be
operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or
Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in
Master Mode until it loses an arbitration or generates a STOP. An SMBus interrupt is generated at the end
of all SMBus byte frames. Note that the position of the ACK interrupt when operating as a receiver
depends on whether hardware ACK generation is enabled. As a receiver, the interrupt for an ACK occurs
before the ACK with hardware ACK generation disabled, and after the ACK when hardware ACK
generation is enabled. As a transmitter, interrupts occur after the ACK, regardless of whether hardware
ACK generation is enabled or not.
22.5.1. Write Sequence (Master)
During a write sequence, an SMBus master writes data to a slave device. The master in this transfer will be
a transmitter during the address byte, and a transmitter during all data bytes. The SMBus interface
generates the START condition and transmits the first byte containing the address of the target slave and
the data direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then
transmits one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated
by the slave. The transfer is ended when the STO bit is set and a STOP is generated. Note that the
interface will switch to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter
interrupt. Figure 22.5 shows a typical master write sequence. Two transmit data bytes are shown, though
any number of bytes may be transmitted. All “data byte transferred” interrupts occur after the ACK cycle in
this mode, regardless of whether hardware ACK generation is enabled.
Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
WA
Data Byte
A
Data Byte
AP
Interrupts with Hardware ACK Disabled (EHACK = 0)
Received by SMBus
Interface
Transmitted by
SMBus Interface
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Figure 22.5. Typical Master Write Sequence
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