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C8051F93X Datasheet, PDF (314/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks
C8051F93x-C8051F92x
26.3.5.2. 9/10/11-bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 9/10/11-bit PWM mode should be varied by writing to an “Auto-
Reload” Register, which is dual-mapped into the PCA0CPHn and PCA0CPLn register locations. The data
written to define the duty cycle should be right-justified in the registers. The auto-reload registers are
accessed (read or written) when the bit ARSEL in PCA0PWM is set to 1. The capture/compare registers
are accessed when ARSEL is set to 0.
When the least-significant N bits of the PCA0 counter match the value in the associated module’s
capture/compare register (PCA0CPn), the output on CEXn is asserted high. When the counter overflows
from the Nth bit, CEXn is asserted low (see Figure 26.9). Upon an overflow from the Nth bit, the COVF flag
is set, and the value stored in the module’s auto-reload register is loaded into the capture/compare
register. The value of N is determined by the CLSEL bits in register PCA0PWM.
The 9, 10 or 11-bit PWM mode is selected by setting the ECOMn and PWMn bits in the PCA0CPMn
register, and setting the CLSEL bits in register PCA0PWM to the desired cycle length (other than 8-bits). If
the MATn bit is set to 1, the CCFn flag for the module will be set each time a comparator match (rising
edge) occurs. The COVF flag in PCA0PWM can be used to detect the overflow (falling edge), which will
occur every 512 (9-bit), 1024 (10-bit) or 2048 (11-bit) PCA clock cycles. The duty cycle for 9/10/11-Bit
PWM Mode is given in Equation 26.2, where N is the number of bits in the PWM cycle.
Important Note About PCA0CPHn and PCA0CPLn Registers: When writing a 16-bit value to the
PCA0CPn registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn
bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Duty Cycle = ---2---N-----–----P----C-----A----0---C----P----n----
2N
Equation 26.3. 9, 10, and 11-Bit PWM Duty Cycle
A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Write to
PCA0CPLn
0
Reset
ENB
Write to
PCA0CPHn ENB
1
PCA0CPMn
P ECCMT P E
WCA A AOWC
MOP P TGMC
1 MPN n n n F
6nnn
n
n
0 00x0 x
R/W when
ARSEL = 1
(Auto-Reload)
PCA0CPH:Ln
(right-justified)
R/W when
ARSEL = 0
(Capture/Compare)
PCA0CPH:Ln
(right-justified)
Enable N-bit Comparator
PCA0PWM
A EC
CC
R CO
LL
SOV
SS
EVF
EE
L
LL
10
x
Set “N” bits:
01 = 9 bits
10 = 10 bits
11 = 11 bits
match S SET Q CEXn Crossbar
R CLR Q
PCA Timebase
PCA0H:L
Overflow of Nth Bit
Figure 26.9. PCA 9, 10 and 11-Bit PWM Mode Diagram
Port I/O
314
Rev. 1.3