C8051F93X Datasheet, PDF (186/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
18.2. Power-Fail (VDD/DC+ Supply Monitor) Reset
C8051F93x-C8051F92x devices have a VDD/DC+ Supply Monitor that is enabled and selected as a reset
source after each power-on or power-fail reset. When enabled and selected as a reset source, any power
down transition or power irregularity that causes VDD/DC+ to drop below V_RST will cause the RST pin to
be driven low and the CIP-51 will be held in a reset state (see Figure 18.3). When VDD/DC+ returns to a
level above V_RST, the CIP-51 will be released from the reset state.
After a power-fail reset, the PORSF flag reads 1, the contents of RAM invalid, and the VDD/DC+ supply
monitor is enabled and selected as a reset source. The enable state of the VDD/DC+ supply monitor and
its selection as a reset source is only altered by power-on and power-fail resets. For example, if the
VDD/DC+ supply monitor is de-selected as a reset source and disabled by software, then a software reset
is performed, the VDD/DC+ supply monitor will remain disabled and de-selected after the reset.
In battery-operated systems, the contents of RAM can be preserved near the end of the battery’s usable
life if the device is placed in sleep mode prior to a power-fail reset occurring. When the device is in sleep
mode, the power-fail reset is automatically disabled and the contents of RAM are preserved as long as the
VBAT supply does not fall below V_POR. A large capacitor can be used to hold the power supply voltage
above V_POR while the user is replacing the battery. Upon waking from sleep mode, the enable and reset
source select state of the VDD/DC+ supply monitor are restored to the value last set by the user.
To allow software early notification that a power failure is about to occur, the VDDOK bit is cleared when
the VDD/DC+ supply falls below the V_WARN threshold. The VDDOK bit can be configured to generate an
interrupt. See Section “12. Interrupt Handler” on page 136 for more details.
Important Note: To protect the integrity of Flash contents, the VDD/DC+ supply monitor must be
enabled and selected as a reset source if software contains routines which erase or write Flash
memory. If the VDD/DC+ supply monitor is not enabled, any erase or write performed on Flash memory
will cause a Flash Error device reset.
V_WARN
V_RST
V_POR
VDD/DC+
VBAT
t
VDDOK
SLEEP
RST
Active Mode
Power-Fail Reset
Sleep Mode
RAM Retained - No Reset
Note: Wakeup signal
required after new
battery insertion
Figure 18.3. Power-Fail Reset Timing Diagram
186
Rev. 1.3