C8051F93X Datasheet, PDF (185/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
18.1. Power-On (VBAT Supply Monitor) Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V_BAT settles above
V_POR. An additional delay occurs before the device is released from reset; the delay decreases as the
V_BAT ramp time increases (V_BAT ramp time is defined as how fast V_BAT ramps from 0 V to V_POR).
Figure 18.3 plots the power-on and V_DD monitor reset timing. For valid ramp times (less than 3 ms), the
power-on reset delay (T_PORDelay) is typically 3 ms (V_BAT = 0.9 V), 7 ms (V_BAT = 1.8 V), or 15 ms (V_BAT =
3.6 V).
Note: The maximum V_DD ramp time is 3 ms; slower ramp times may cause the device to be released from reset
before V_BAT reaches the V_POR level.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000), software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be undefined after a power-on reset.
~0.8
V_POR
0.6
VBAT
~0.5
See specification
table for min/max
voltages.
Logic HIGH ^RST
Logic LOW
T_PORDelay
t
T_PORDelay
Power-On
Reset
Power-On
Reset
Figure 18.2. Power-Fail Reset Timing Diagram
Rev. 1.3
185