C8051F93X Datasheet, PDF (7/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
21.5.Special Function Registers for Accessing and Configuring Port I/O .............. 229
22. SMBus ................................................................................................................... 238
22.1.Supporting Documents ................................................................................... 239
22.2.SMBus Configuration...................................................................................... 239
22.3.SMBus Operation ........................................................................................... 240
22.3.1.Transmitter Vs. Receiver........................................................................ 240
22.3.2.Arbitration............................................................................................... 241
22.3.3.Clock Low Extension.............................................................................. 241
22.3.4.SCL Low Timeout................................................................................... 241
22.3.5.SCL High (SMBus Free) Timeout .......................................................... 241
22.4.Using the SMBus............................................................................................ 242
22.4.1.SMBus Configuration Register............................................................... 243
22.4.2.SMB0CN Control Register ..................................................................... 246
22.4.3.Hardware Slave Address Recognition ................................................... 249
22.4.4.Data Register ......................................................................................... 251
22.5.SMBus Transfer Modes.................................................................................. 252
22.5.1.Write Sequence (Master) ....................................................................... 252
22.5.2.Read Sequence (Master) ....................................................................... 253
22.5.3.Write Sequence (Slave) ......................................................................... 254
22.5.4.Read Sequence (Slave) ......................................................................... 255
22.6.SMBus Status Decoding................................................................................. 255
23. UART0.................................................................................................................... 260
23.1.Enhanced Baud Rate Generation................................................................... 261
23.2.Operational Modes ......................................................................................... 262
23.2.1.8-Bit UART ............................................................................................. 262
23.2.2.9-Bit UART ............................................................................................. 263
23.3.Multiprocessor Communications .................................................................... 263
24. Enhanced Serial Peripheral Interface (SPI0 and SPI1)...................................... 268
24.1.Signal Descriptions......................................................................................... 269
24.1.1.Master Out, Slave In (MOSI).................................................................. 269
24.1.2.Master In, Slave Out (MISO).................................................................. 269
24.1.3.Serial Clock (SCK) ................................................................................. 269
24.1.4.Slave Select (NSS) ................................................................................ 269
24.2.SPI Master Mode Operation ........................................................................... 270
24.3.SPI Slave Mode Operation ............................................................................. 272
24.4.SPI Interrupt Sources ..................................................................................... 272
24.5.Serial Clock Phase and Polarity ..................................................................... 273
24.6.SPI Special Function Registers ...................................................................... 275
25. Timers.................................................................................................................... 283
25.1.Timer 0 and Timer 1 ....................................................................................... 285
25.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 285
25.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 286
25.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 287
25.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 288
25.2.Timer 2 .......................................................................................................... 293
Rev. 1.3
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