C8051F93X Datasheet, PDF (218/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
21.1.3. Interfacing Port I/O to 5 V and 3.3 V Logic
All Port I/O configured for digital, open-drain operation are capable of interfacing to digital logic operating
at a supply voltage higher than 4.5 V and less than 5.25 V. When the supply voltage is in the range of 1.8
to 2.2 V, the I/O may also interface to digital logic operating between 3.0 to 3.6 V if the input signal
frequency is less than 12.5 MHz or less than 25 MHz if the signal rise time (10% to 90%) is less than
1.2 ns. When operating at a supply voltage above 2.2 V, the device should not interface to 3.3 V logic;
however, interfacing to 5 V logic is permitted. An external pull-up resistor to the higher supply voltage is
typically required for most systems.
Important Notes:
• When interfacing to a signal that is between 4.5 and 5.25 V, the maximum clock frequency that may be
input on a GPIO pin is 12.5 MHz. The exception to this rule is when routing an external CMOS clock to
P0.3, in which case, a signal up to 25 MHz is valid as long as the rise time (10% to 90%) is shorter
than 1.8 ns.
• When the supply voltage is less than 2.2 V and interfacing to a signal that is between 3.0 and 3.6 V,
the maximum clock frequency that may be input on a GPIO pin is 3.125 MHz. The exception to this
rule is when routing an external CMOS clock to P0.3, in which case, a signal up to 25 MHz is valued as
long as the rise time (10% to 90%) is shorter than 1.2 ns.
• In a multi-voltage interface, the external pull-up resistor should be sized to allow a current of at least
150 μA to flow into the Port pin when the supply voltage is between (VDD/DC+ plus 0.4 V) and
(VDD/DC+ plus 1.0 V). Once the Port pad voltage increases beyond this range, the current flowing into
the Port pin is minimal.
These guidelines only apply to multi-voltage interfaces. Port I/Os may always interface to digital logic
operating at the same supply voltage.
21.1.4. Increasing Port I/O Drive Strength
Port I/O output drivers support a high and low drive strength; the default is low drive strength. The drive
strength of a Port I/O can be configured using the PnDRV registers. See Section “4. Electrical
Characteristics” on page 45 for the difference in output drive strength between the two modes.
21.2. Assigning Port I/O Pins to Analog and Digital Functions
Port I/O pins P0.0–P2.6 can be assigned to various analog, digital, and external interrupt functions. The
Port pins assuaged to analog functions should be configured for analog I/O and Port pins assuaged to dig-
ital or external interrupt functions should be configured for digital I/O.
21.2.1. Assigning Port I/O Pins to Analog Functions
Table 21.1 shows all available analog functions that need Port I/O assignments. Port pins selected for
these analog functions should have their digital drivers disabled (PnMDOUT.n = 0 and Port Latch =
1) and their corresponding bit in PnSKIP set to 1. This reserves the pin for use by the analog function
and does not allow it to be claimed by the Crossbar. Table 21.1 shows the potential mapping of Port I/O to
each analog function.
Table 21.1. Port I/O Assignment for Analog Functions
Analog Function
ADC Input
Comparator0 Input
Potentially
Assignable Port Pins
P0.0–P2.6
P0.0–P2.6
SFR(s) used for
Assignment
ADC0MX, PnSKIP
CPT0MX, PnSKIP
218
Rev. 1.3