C8051F93X Datasheet, PDF (121/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
10.5.3. Split Mode with Bank Select
When EMI0CF.[3:2] are set to 10, the XRAM memory map is split into two areas, on-chip space and off-
chip space.
• Effective addresses below the on-chip XRAM boundary will access on-chip XRAM space.
• Effective addresses above the on-chip XRAM boundary will access off-chip space.
• 8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-
chip or off-chip. The upper 4-bits of the Address Bus A[11:8] are determined by EMI0CN, and the lower
8-bits of the Address Bus A[7:0] are determined by R0 or R1. All 12-bits of the Address Bus A[11:0]
are driven in “Bank Select” mode.
• 16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-
chip or off-chip, and the full 12-bits of the Address Bus A[11:0] are driven during the off-chip transac-
tion.
10.5.4. External Only
When EMI0CF[3:2] are set to 11, all MOVX operations are directed to off-chip space. On-chip XRAM is not
visible to the CPU. This mode is useful for accessing off-chip memory located between 0x0000 and the on-
chip XRAM boundary.
• 8-bit MOVX operations ignore the contents of EMI0CN. The upper Address bits A[11:8] are not driven
(identical behavior to an off-chip access in “Split Mode without Bank Select” described above). This
allows the user to manipulate the upper address bits at will by setting the Port state directly. The lower
8-bits of the effective address A[7:0] are determined by the contents of R0 or R1.
• 16-bit MOVX operations use the contents of DPTR to determine the effective address A[11:0]. The full
12-bits of the Address Bus A[11:0] are driven during the off-chip transaction.
10.6. External Memory Interface Timing
The timing parameters of the External Memory Interface can be configured to enable connection to
devices having different setup and hold time requirements. The Address Setup time, Address Hold time,
RD and WR strobe widths, and in multiplexed mode, the width of the ALE pulse are all programmable in
units of SYSCLK periods through EMI0TC, shown in SFR Definition 10.3, and EMI0CF[1:0].
The timing for an off-chip MOVX instruction can be calculated by adding 4 SYSCLK cycles to the timing
parameters defined by the EMI0TC register. Assuming non-multiplexed operation, the minimum execution
time for an off-chip XRAM operation is 5 SYSCLK cycles (1 SYSCLK for RD or WR pulse + 4 SYSCLKs).
For multiplexed operations, the Address Latch Enable signal will require a minimum of 2 additional
SYSCLK cycles. Therefore, the minimum execution time of an off-chip XRAM operation in multiplexed
mode is 7 SYSCLK cycles (2 SYSCLKs for ALE, 1 for RD or WR + 4 SYSCLKs). The programmable setup
and hold times default to the maximum delay settings after a reset.
Table 10.1 lists the ac parameters for the External Memory Interface, and Figure 10.1 through Figure 10.6
show the timing diagrams for the different External Memory Interface modes and MOVX operations. See
Section “21. Port Input/Output” on page 216 to determine which port pins are mapped to the ADDR[11:8],
AD[7:0], ALE, RD, and WR signals.
Rev. 1.3
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