C8051F93X Datasheet, PDF (278/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 24.3. SPInCKR: SPI Clock Rate
Bit
7
6
5
4
3
2
1
0
Name
SCRn[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Addresses: SPI0CKR = 0xA2, SPI1CKR = 0x85 
SFR Pages: SPI0CKR = 0x0, SPI1CKR = 0x0
Bit
Name
Function
7:0
SCRn
SPI Clock Rate.
These bits determine the frequency of the SCK output when the SPI module is
configured for master mode operation. The SCK clock frequency is a divided
version of the system clock, and is given in the following equation, where SYSCLK
is the system clock frequency and SPInCKR is the 8-bit value held in the SPInCKR
register.
f_SCK = _2----------_--S----P---SI--n-Y--C--S--K--C--R--L--[-K-7---:--0---]---+-----1----_
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPInCKR = 0x04,
f_SCK = _{2---2--}-0---0-_--40---0--+-0---0-1---_
f_SCK = 200kHz
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Rev. 1.3