C8051F93X Datasheet, PDF (303/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 25.14. TMR3RLL: Timer 3 Reload Register Low Byte
Bit
7
6
5
4
3
2
1
0
Name
TMR3RLL[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x92
Bit
Name
Function
7:0 TMR3RLL[7:0] Timer 3 Reload Register Low Byte.
TMR3RLL holds the low byte of the reload value for Timer 3.
SFR Definition 25.15. TMR3RLH: Timer 3 Reload Register High Byte
Bit
7
6
5
4
3
2
1
0
Name
TMR3RLH[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x93
Bit
Name
Function
7:0 TMR3RLH[7:0] Timer 3 Reload Register High Byte.
TMR3RLH holds the high byte of the reload value for Timer 3.
Rev. 1.3
303