C8051F93X Datasheet, PDF (198/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 19.2. OSCICN: Internal Oscillator Control
Bit
7
6
5
4
3
2
1
0
Name IOSCEN IFRDY
Reserved[5:0]
Type
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
1
1
1
1
SFR Page = 0x0; SFR Address = 0xB2
Bit Name
Function
7 IOSCEN Internal Oscillator Enable.
0: Internal oscillator disabled.
1: Internal oscillator enabled.
6
IFRDY Internal Oscillator Frequency Ready Flag.
0: Internal oscillator is not running at its programmed frequency.
1: Internal oscillator is running at its programmed frequency.
5:0 Reserved Reserved.
Read = 001111b. Must Write 001111b.
Note: It is recommended to use read-modify-write operations such as ORL and ANL to set or clear the enable bit of
this register.
SFR Definition 19.3. OSCICL: Internal Oscillator Calibration
Bit
7
6
5
Name
Type
Reset
SSE
R/W
0
R
Varies
R/W
Varies
SFR Page = 0x0; SFR Address = 0xB3
4
3
2
R/W
OSCICL[6:0]
R/W
R/W
Varies
Varies
Varies
1
R/W
Varies
0
R/W
Varies
Bit Name
Function
7
SSE Spread Spectrum Enable.
0: Spread Spectrum clock dithering disabled.
1: Spread Spectrum clock dithering enabled.
6:0 OSCICL Internal Oscillator Calibration.
Factory calibrated to obtain a frequency of 24.5 MHz. Incrementing this register
decreases the oscillator frequency and decrementing this register increases the
oscillator frequency. The step size is approximately 1% of the calibrated frequency.
The recommended calibration frequency range is between 16 and 24.5 MHz.
198
Rev. 1.3