C8051F93X Datasheet, PDF (156/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 13.1. PSCTL: Program Store R/W Control
Bit
7
6
5
4
3
2
1
0
Name
SFLE
PSEE
PSWE
Type
R
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page =0x0; SFR Address = 0x8F
Bit Name
Function
7:3 Unused Unused.
Read = 00000b, Write = don’t care.
2 SFLE Scratchpad Flash Memory Access Enable.
When this bit is set, Flash MOVC reads and MOVX writes from user software are
directed to the Scratchpad Flash sector. Flash accesses outside the address range
0x0000-0x03FF should not be attempted and may yield undefined results when SFLE
is set to 1.
0: Flash access from user software directed to the Program/Data Flash sector.
1: Flash access from user software directed to the Scratchpad Sector.
1 PSEE Program Store Erase Enable.
Setting this bit (in combination with PSWE) allows an entire page of Flash program
memory to be erased. If this bit is logic 1 and Flash writes are enabled (PSWE is logic
1), a write to Flash memory using the MOVX instruction will erase the entire page that
contains the location addressed by the MOVX instruction. The value of the data byte
written does not matter.
0: Flash program memory erasure disabled.
1: Flash program memory erasure enabled.
0 PSWE Program Store Write Enable.
Setting this bit allows writing a byte of data to the Flash program memory using the
MOVX write instruction. The Flash location should be erased before writing data.
0: Writes to Flash program memory disabled.
1: Writes to Flash program memory enabled; the MOVX write instruction targets Flash
memory.
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Rev. 1.3