C8051F93X Datasheet, PDF (120/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
10.5. External Memory Interface Operating Modes
The external data memory space can be configured in one of four operating modes, shown in Figure 10.3,
based on the EMIF Mode bits in the EMI0CF register (SFR Definition 10.2). These modes are summarized
below. Timing diagrams for the different modes can be found in Section “10.6. External Memory Interface
Timing” on page 121.
10.5.1. Internal XRAM Only
When EMI0CF.[3:2] are set to 00, all MOVX instructions will target the internal XRAM space on the device.
Memory accesses to addresses beyond the populated space will wrap, and will always target on-chip
XRAM. As an example, if the entire address space is consecutively written and the data pointer is
incremented after each write, the write pointer will always point to the first byte of on-chip XRAM after the
last byte of on-chip XRAM has been written.
• 8-bit MOVX operations use the contents of EMI0CN to determine the high-byte of the effective address
and R0 or R1 to determine the low-byte of the effective address.
• 16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address.
10.5.2. Split Mode without Bank Select
When EMI0CF.[3:2] are set to 01, the XRAM memory map is split into two areas, on-chip space and off-
chip space.
• Effective addresses below the on-chip XRAM boundary will access on-chip XRAM space.
• Effective addresses above the on-chip XRAM boundary will access off-chip space.
• 8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-
chip or off-chip. However, in the “No Bank Select” mode, an 8-bit MOVX operation will not drive the
upper 4-bits A[11:8] of the Address Bus during an off-chip access. This allows the user to manip-
ulate the upper address bits at will by setting the Port state directly via the port latches. This behavior
is in contrast with “Split Mode with Bank Select” described below. The lower 8-bits of the Address Bus
A[7:0] are driven, determined by R0 or R1.
• 16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-
chip or off-chip, and unlike 8-bit MOVX operations, the full 12-bits of the Address Bus A[11:0] are
driven during the off-chip transaction.
EMI0CF[3:2] = 00
On-Chip XRAM
EMI0CF[3:2] = 01
0xFFFF
EMI0CF[3:2] = 10
0xFFFF
EMI0CF[3:2] = 11
0xFFFF
0xFFFF
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
Off-Chip
Memory
(No Bank Select)
Off-Chip
Memory
(Bank Select)
Off-Chip
Memory
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
0x0000
On-Chip XRAM
0x0000
0x0000
Figure 10.3. EMIF Operating Modes
0x0000
120
Rev. 1.3