C8051F93X Datasheet, PDF (138/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Table 12.1. Interrupt Summary
Interrupt Source
Interrupt
Vector
Priority
Order
Pending Flag
Enable Flag
Priority
Control
Reset
External Interrupt 0 (INT0)
Timer 0 Overflow
External Interrupt 1 (INT1)
Timer 1 Overflow
UART0
Timer 2 Overflow
0x0000
0x0003
0x000B
0x0013
0x001B
0x0023
0x002B
SPI0
0x0033
SMB0
0x003B
SmaRTClock Alarm
0x0043
ADC0 Window Comparator 0x004B
ADC0 End of Conversion
0x0053
Programmable Counter Array 0x005B
Comparator0
0x0063
Comparator1
0x006B
Timer 3 Overflow
VDD/DC+ Supply Monitor
Early Warning
Port Match
0x0073
0x007B
0x0083
SmaRTClock Oscillator Fail 0x008B
SPI1
0x0093
Top None
N/A N/A
Always
Enabled
Always
Highest
0 IE0 (TCON.1)
Y Y EX0 (IE.0) PX0 (IP.0)
1 TF0 (TCON.5)
Y Y ET0 (IE.1) PT0 (IP.1)
2 IE1 (TCON.3)
Y Y EX1 (IE.2) PX1 (IP.2)
3 TF1 (TCON.7)
Y Y ET1 (IE.3) PT1 (IP.3)
4
RI0 (SCON0.0)
TI0 (SCON0.1)
Y N ES0 (IE.4) PS0 (IP.4)
5
TF2H (TMR2CN.7)
TF2L (TMR2CN.6)
Y N ET2 (IE.5) PT2 (IP.5)
SPIF (SPI0CN.7)
6
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
Y N ESPI0 (IE.6) PSPI0 (IP.6)
RXOVRN (SPI0CN.4)
7 SI (SMB0CN.0)
YN
ESMB0
(EIE1.0)
PSMB0
(EIP1.0)
8 ALRM (RTC0CN.2)*
NN
EARTC0
(EIE1.1)
PARTC0
(EIP1.1)
9
AD0WINT (ADC0CN.3)
Y
N
EWADC0
(EIE1.2)
PWADC0
(EIP1.2)
10 AD0INT (ADC0STA.5)
YN
EADC0
(EIE1.3)
PADC0
(EIP1.3)
11
CF (PCA0CN.7)
CCFn (PCA0CN.n)
YN
EPCA0
(EIE1.4)
PPCA0
(EIP1.4)
12
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
NN
ECP0
(EIE1.5)
PCP0
(EIP1.5)
13
CP1FIF (CPT1CN.4)
CP1RIF (CPT1CN.5)
NN
ECP1
(EIE1.6)
PCP1
(EIP1.6)
14
TF3H (TMR3CN.7)
TF3L (TMR3CN.6)
NN
ET3
(EIE1.7)
PT3
(EIP1.7)
15 _{VDDOK (VDM0CN.5)}¹
EWARN
(EIE2.0)
PWARN
(EIP2.0)
16 None
EMAT
(EIE2.1)
PMAT
(EIP2.1)
17
OSCFAIL (RTC0CN.5)^{2 N N}
ERTC0F
(EIE2.2)
PFRTC0F
(EIP2.2)
SPIF (SPI1CN.7)
18
WCOL (SPI1CN.6)
MODF (SPI1CN.5)
NN
ESPI1
(EIE2.3)
PSPI1
(EIP2.3)
RXOVRN (SPI1CN.4)
Notes:
1. Indicates a read-only interrupt pending flag. The interrupt enable may be used to prevent software from
vectoring to the associated interrupt service routine.
2. Indicates a register located in an indirect memory space.
138
Rev. 1.3