C8051F93X Datasheet, PDF (215/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Internal Register Definition 20.8. CAPTUREn: SmaRTClock Timer Capture
Bit
7
6
5
4
3
2
1
0
Name
CAPTURE[31:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SmaRTClock Addresses: CAPTURE0 = 0x00; CAPTURE1 = 0x01; CAPTURE2 =0x02; CAPTURE3: 0x03.
Bit
Name
Function
7:0 CAPTURE[31:0] SmaRTClock Timer Capture.
These 4 registers (CAPTURE3–CAPTURE0) are used to read or set the 32-bit
SmaRTClock timer. Data is transferred to or from the SmaRTClock timer when
the RTC0SET or RTC0CAP bits are set.
Note: The least significant bit of the timer capture value is in CAPTURE0.0.
Internal Register Definition 20.9. ALARMn: SmaRTClock Alarm Programmed Value
Bit
7
6
5
4
3
2
1
0
Name
ALARM[31:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SmaRTClock Addresses: ALARM0 = 0x08; ALARM1 = 0x09; ALARM2 = 0x0A; ALARM3 = 0x0B
Bit
Name
Function
7:0 ALARM[31:0] SmaRTClock Alarm Programmed Value.
These 4 registers (ALARM3–ALARM0) are used to set an alarm event for the
SmaRTClock timer. The SmaRTClock alarm should be disabled (RTC0AEN=0)
when updating these registers.
Note: The least significant bit of the alarm programmed value is in ALARM0.0.
Rev. 1.3
215