C8051F93X Datasheet, PDF (72/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
System Clock
Convert Start
(AD0BUSY or Timer
Overflow)
Post-Tracking
AD0TM = 01
AD0EN = 0
Dual-Tracking
AD0TM = 11
AD0EN = 0
Powered
Down
Power-Up
and Idle
TC TC TC TC
Powered
Down
Power-Up
and Track
TC TC TC TC
AD0PWR
Powered
Down
Powered
Down
Post-Tracking
AD0TM = 01
AD0EN = 1
Dual-Tracking
AD0TM = 11
AD0EN = 1
Idle
TC TC TC TC
Track T C T C T C T C
Idle
Track
T = Tracking
C = Converting
Power-Up
and Idle
T C..
Power-Up
and Track
T C..
T C T C T C..
T C T C T C..
Convert Start
(CNVSTR)
Post-Tracking
AD0TM = 01
AD0EN = 0
Dual-Tracking
AD0TM = 11
AD0EN = 0
Powered
Down
Power-Up
and Idle
TC
Powered
Down
Power-Up
and Track
TC
AD0PWR
Powered
Down
Powered
Down
Power-Up
and Idle
T C..
Power-Up
and Track
T C..
Post-Tracking
AD0TM = 01
AD0EN = 1
Dual-Tracking
AD0TM = 11
AD0EN = 1
Idle
TC
Track T C
Idle
Track
TC
Idle..
T C Track..
T = Tracking
C = Converting
Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4
72
Rev. 1.3