C8051F93X Datasheet, PDF (107/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Table 8.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
Description
Bytes
ANL C, /bit
AND complement of direct bit to Carry
2
ORL C, bit
OR direct bit to carry
2
ORL C, /bit
OR complement of direct bit to Carry
2
MOV C, bit
Move direct bit to Carry
2
MOV bit, C
Move Carry to direct bit
2
JC rel
Jump if Carry is set
2
JNC rel
Jump if Carry is not set
2
JB bit, rel
Jump if direct bit is set
3
JNB bit, rel
Jump if direct bit is not set
3
JBC bit, rel
Jump if direct bit is set and clear bit
3
Program Branching
ACALL addr11
Absolute subroutine call
2
LCALL addr16
Long subroutine call
3
RET
Return from subroutine
1
RETI
Return from interrupt
1
AJMP addr11
Absolute jump
2
LJMP addr16
Long jump
3
SJMP rel
Short jump (relative address)
2
JMP @A+DPTR
Jump indirect relative to DPTR
1
JZ rel
Jump if A equals zero
2
JNZ rel
Jump if A does not equal zero
2
CJNE A, direct, rel
Compare direct byte to A and jump if not equal
3
CJNE A, #data, rel
Compare immediate to A and jump if not equal
3
CJNE Rn, #data, rel
Compare immediate to Register and jump if not
equal
3
CJNE @Ri, #data, rel
Compare immediate to indirect and jump if not
equal
3
DJNZ Rn, rel
Decrement Register and jump if not zero
2
DJNZ direct, rel
Decrement direct byte and jump if not zero
3
NOP
No operation
1
Clock
Cycles
2
2
2
2
2
2/3
2/3
3/4
3/4
3/4
3
4
5
5
3
4
3
3
2/3
2/3
4/5
3/4
3/4
4/5
2/3
3/4
1
Rev. 1.3
107