C8051F93X Datasheet, PDF (166/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 14.2. PCON: Power Management Control Register
Bit
7
6
5
4
3
Name
Type
Reset
0
0
GF[5:0]
R/W
0
0
0
SFR Page = All Pages; SFR Address = 0x87
Bit Name
Description
7:2 GF[5:0] General Purpose Flags
1
STOP Stop Mode Select
0
IDLE Idle Mode Select
Write
Sets the logic value.
Writing 1 places the
device in Stop Mode.
Writing 1 places the
device in Idle Mode.
2
1
0
STOP
IDLE
W
W
0
0
0
Read
Returns the logic value.
N/A
N/A
14.8. Power Management Specifications
See Table 4.5 on page 60 for detailed Power Management Specifications.
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Rev. 1.3