C8051F93X Datasheet, PDF (9/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
List of Figures
Figure 1.1. C8051F930 Block Diagram .................................................................... 18
Figure 1.2. C8051F931 Block Diagram .................................................................... 18
Figure 1.3. C8051F920 Block Diagram .................................................................... 19
Figure 1.4. C8051F921 Block Diagram .................................................................... 19
Figure 1.5. Port I/O Functional Block Diagram ......................................................... 21
Figure 1.6. PCA Block Diagram................................................................................ 22
Figure 1.7. ADC0 Functional Block Diagram............................................................ 23
Figure 1.8. ADC0 Multiplexer Block Diagram ........................................................... 24
Figure 1.9. Comparator 0 Functional Block Diagram ............................................... 25
Figure 1.10. Comparator 1 Functional Block Diagram ............................................. 25
Figure 3.1. QFN-32 Pinout Diagram (Top View) ...................................................... 31
Figure 3.2. QFN-24 Pinout Diagram (Top View) ...................................................... 32
Figure 3.3. LQFP-32 Pinout Diagram (Top View)..................................................... 33
Figure 3.4. QFN-32 Package Marking Diagram ....................................................... 34
Figure 3.5. QFN-24 Package Marking Diagram ....................................................... 35
Figure 3.6. LQFP-32 Package Marking Diagram ..................................................... 36
Figure 3.7. QFN-32 Package Drawing ..................................................................... 37
Figure 3.8. Typical QFN-32 Landing Diagram.......................................................... 38
Figure 3.9. QFN-24 Package Drawing ..................................................................... 40
Figure 3.10. Typical QFN-24 Landing Diagram........................................................ 41
Figure 3.11. LQFP-32 Package Diagram ................................................................. 43
Figure 3.12. Typical LQFP-32 Landing Diagram ...................................................... 44
Figure 4.1. Active Mode Current (External CMOS Clock) ........................................ 48
Figure 4.2. Idle Mode Current (External CMOS Clock) ............................................ 49
Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 2 V) ... 50
Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 3 V) ... 51
Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC+ = 2 V).... 52
Figure 4.6. Typical One-Cell Suspend Mode Current............................................... 53
Figure 4.7. Typical VOH Curves, 1.8–3.6 V ............................................................. 55
Figure 4.8. Typical VOH Curves, 0.9–1.8 V ............................................................. 56
Figure 4.9. Typical VOL Curves, 1.8–3.6 V .............................................................. 57
Figure 4.10. Typical VOL Curves, 0.9–1.8 V ............................................................ 58
Figure 5.1. ADC0 Functional Block Diagram............................................................ 67
Figure 5.2. 10-Bit ADC Track and Conversion Example Timing (BURSTEN = 0).... 70
Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4 ................... 72
Figure 5.4. ADC0 Equivalent Input Circuits .............................................................. 73
Figure 5.5. ADC Window Compare Example: Right-Justified Single-Ended Data ... 83
Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data...... 83
Figure 5.7. ADC0 Multiplexer Block Diagram ........................................................... 84
Figure 5.8. Temperature Sensor Transfer Function ................................................. 86
Figure 5.9. Temperature Sensor Error with 1-Point Calibration (V_REF = 1.68 V) ..... 87
Figure 5.10. Voltage Reference Functional Block Diagram...................................... 89
Figure 7.1. Comparator 0 Functional Block Diagram ............................................... 93
Rev. 1.3
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