C8051F93X Datasheet, PDF (119/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
A[11:8]
ADDRESS BUS
74HC373
E
ALE
G
M
AD[7:0]
ADDRESS/DATA BUS D
V_DD
Q
I
(Optional)
F
8
WR
RD
A[11:8]
A[7:0]
4K X 8
SRAM
I/O[7:0]
CE
WE
OE
Figure 10.2. Multiplexed to Non-Multiplexed Configuration Example
Rev. 1.3
119