C8051F93X Datasheet, PDF (101/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 7.5. CPT0MX: Comparator0 Input Channel Select
Bit
7
6
5
4
3
2
1
0
Name
CMX0N[3:0]
CMX0P[3:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
SFR Page = 0x0; SFR Address = 0x9F
Bit Name
Function
7:4 CMX0N Comparator0 Negative Input Selection.
Selects the negative input channel for Comparator0.
0000:
0001:
0010:
0011:
P0.1
P0.3
P0.5
P0.7
1000:
1001:
1010:
1011:
0100:
P1.1
1100:
0101:
P1.3
1101:
0110:
P1.5
1110:
0111:
P1.7 (C8051F920/30
Only)
1111:
3:0 CMX0P Comparator0 Positive Input Selection.
Selects the positive input channel for Comparator0.
0000:
P0.0
1000:
0001:
P0.2
1001:
0010:
P0.4
1010:
0011:
P0.6
1011:
0100:
P1.0
1100:
0101:
0110:
0111:
P1.2
P1.4
P1.6
1101:
1110:
1111:
P2.1 (C8051F920/30 Only)
P2.3 (C8051F920/30 Only)
P2.5 (C8051F920/30 Only)
Reserved
Capacitive Touch Sense 
Compare
VDD/DC+ divided by 2
Digital Supply Voltage
Ground
P2.0 (C8051F920/30 Only)
P2.2 (C8051F920/30 Only)
P2.4 (C8051F920/30 Only)
P2.6 (C8051F920/30 Only)
Capacitive Touch Sense 
Compare
VDD/DC+ divided by 2
VBAT Supply Voltage
VDD/DC+ Supply Voltage
Rev. 1.3
101