C8051F93X Datasheet, PDF (235/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 21.17. P1DRV: Port1 Drive Strength
Bit
7
6
5
4
3
2
1
0
Name
P1DRV[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0xA5
Bit Name
Function
7:0 P1DRV[7:0] Drive Strength Configuration Bits for P1.7–P1.0 (respectively).
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P1.n Output has low output drive strength.
1: Corresponding P1.n Output has high output drive strength.
Note: Pin P1.7 is only available in 32-pin devices.
SFR Definition 21.18. P2: Port2
Bit
7
6
5
4
3
2
1
0
Name
P2[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Page = All Pages; SFR Address = 0xA0; Bit-Addressable
Bit
Name
Description
Read
Write
7:0 P2[7:0] Port 2 Data.
0: Set output latch to logic 0: P2.n Port pin is logic
Sets the Port latch logic
LOW.
LOW.
value or reads the Port pin ^{1: Set output latch to logic 1: P2.n Port pin is logic}
logic state in Port cells con- ^HIGH.
HIGH.
figured for digital I/O.
Note: Pins P2.0-P2.6 are only available in 32-pin devices.
Rev. 1.3
235