C8051F93X Datasheet, PDF (17/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
1. System Overview
C8051F93x-C8051F92x devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted
features are listed below. Refer to Table 2.1 for specific product feature selection and part ordering num-
bers.
• Single/Dual Battery operation with on-chip dc-dc boost converter.
• High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)
• In-system, full-speed, non-intrusive debug interface (on-chip)
• True 10-bit 300 ksps 23-channel single-ended ADC with analog multiplexer
• 6-Bit Programmable Current Reference
• Precision programmable 24.5 MHz internal oscillator with spread spectrum technology.
• 64 kB or 32 kB of on-chip Flash memory
• 4352 bytes of on-chip RAM
• SMBus/I²C, Enhanced UART, and two Enhanced SPI serial interfaces implemented in hardware
• Four general-purpose 16-bit timers
• Programmable Counter/Timer Array (PCA) with six capture/compare modules and Watchdog Timer
function
• On-chip Power-On Reset, V_DD Monitor, and Temperature Sensor
• Two On-chip Voltage Comparators with 23 Touch Sense inputs.
• 24 or 16 Port I/O (5 V tolerant)
With on-chip Power-On Reset, V_DD monitor, Watchdog Timer, and clock oscillator, the C8051F93x-
C8051F92x devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can be repro-
grammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051
firmware. User software has complete control of all peripherals, and may individually shut down any or all
peripherals for power savings.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging with-
out occupying package pins.
Each device is specified for 0.9 to 1.8 V or 1.8 to 3.6 V operation over the industrial temperature range 
(–40 to +85 °C). The Port I/O and RST pins are tolerant of input signals up to 5 V. The C8051F930/20 are
available in 32-pin QFN or LQFP packages and the C8051F931/21 are available in a 24-pin QFN package.
Both package options are lead-free and RoHS compliant. See Table 2.1 for ordering information. Block
diagrams are included in Figure 1.1 through Figure 1.4.
Rev. 1.3
17