C8051F93X Datasheet, PDF (129/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
11. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the C8051F93x-C8051F92x's resources and
peripherals. The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well
as implementing additional SFRs used to configure and access the sub-systems unique to the
C8051F93x-C8051F92x. This allows the addition of new functionality while retaining compatibility with the
MCS-51™ instruction set. Table 11.1 and Table 11.2 list the SFRs implemented in the C8051F93x-
C8051F92x device family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 11.3, for a detailed description of each register.
Table 11.1. Special Function Register (SFR) Memory Map (Page 0x0)
F8 SPI0CN PCA0L PCA0H PCA0CPL0 PCA0CPH0 PCA0CPL4
F0 B
P0MDIN P1MDIN P2MDIN SMB0ADR SMB0ADM
E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3
E0 ACC
XBR0
XBR1
XBR2
IT01CF
D8 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3
D0 PSW REF0CN PCA0CPL5 PCA0CPH5 P0SKIP
P1SKIP
C8 TMR2CN REG0CN TMR2RLL TMR2RLH TMR2L
TMR2H
C0 SMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH ADC0LTL
B8 IP IREF0CN ADC0AC ADC0MX ADC0CF ADC0L
B0 SPI1CN OSCXCN OSCICN OSCICL
PMU0CF
A8 IE
CLKSEL EMI0CN EMI0CF RTC0ADR RTC0DAT
A0 P2 SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT
98 SCON0 SBUF0 CPT1CN CPT0CN CPT1MD CPT0MD
90 P1 TMR3CN TMR3RLL TMR3RLH TMR3L
TMR3H
88 TCON TMOD
TL0
TL1
TH0
TH1
80 P0
SP
DPL
DPH SPI1CFG SPI1CKR
0(8)
1(9)
2(A)
3(B)
4(C)
5(D)
(bit addressable)
PCA0CPH4 VDM0CN
EIP1
EIP2
PCA0CPH3 RSTSRC
EIE1
EIE2
PCA0CPM4 PCA0PWM
P2SKIP
P0MAT
PCA0CPM5 P1MAT
ADC0LTH P0MASK
ADC0H P1MASK
FLSCL
FLKEY
RTC0KEY EMI0TC
P2MDOUT SFRPAGE
CPT1MX CPT0MX
DC0CF
DC0CN
CKCON
PSCTL
SPI1DAT
PCON
6(E)
7(F)
Rev. 1.3
129