C8051F93X Datasheet, PDF (37/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Figure 3.7. QFN-32 Package Drawing
Table 3.2. QFN-32 Package Dimensions
Dimension
A
A1
b
D
D2
e
E
Min
Typ
Max
0.80
0.9
1.00
0.00 0.02 0.05
0.18 0.25 0.30
5.00 BSC
3.20 3.30 3.40
0.50 BSC
5.00 BSC
Dimension Min
Typ
Max
E2
3.20 3.30 3.40
L
0.30 0.40 0.50
L1
0.00
—
0.15
aaa
—
—
0.15
bbb
—
—
0.10
ddd
—
—
0.05
eee
—
—
0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except
for custom features D2, E2, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
Rev. 1.3
37