C8051F93X Datasheet, PDF (10/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Figure 7.2. Comparator 1 Functional Block Diagram ............................................... 94
Figure 7.3. Comparator Hysteresis Plot ................................................................... 95
Figure 7.4. CPn Multiplexer Block Diagram............................................................ 100
Figure 8.1. CIP-51 Block Diagram.......................................................................... 103
Figure 9.1. C8051F93x-C8051F92x Memory Map ................................................. 112
Figure 9.2. Flash Program Memory Map................................................................ 113
Figure 10.1. Multiplexed Configuration Example.................................................... 118
Figure 10.2. Multiplexed to Non-Multiplexed Configuration Example..................... 119
Figure 10.3. EMIF Operating Modes ...................................................................... 120
Figure 10.4. Multiplexed 16-bit MOVX Timing........................................................ 125
Figure 10.5. Multiplexed 8-bit MOVX without Bank Select Timing ......................... 126
Figure 10.6. Multiplexed 8-bit MOVX with Bank Select Timing .............................. 127
Figure 13.1. Flash Program Memory Map.............................................................. 150
Figure 14.1. C8051F93x-C8051F92x Power Distribution....................................... 160
Figure 15.1. CRC0 Block Diagram ......................................................................... 167
Figure 15.2. Bit Reverse Register .......................................................................... 174
Figure 16.1. DC-DC Converter Block Diagram....................................................... 175
Figure 16.2. DC-DC Converter Configuration Options ........................................... 178
Figure 18.1. Reset Sources.................................................................................... 184
Figure 18.2. Power-Fail Reset Timing Diagram ..................................................... 185
Figure 18.3. Power-Fail Reset Timing Diagram ..................................................... 186
Figure 19.1. Clocking Sources Block Diagram ....................................................... 191
Figure 19.2. 25 MHz External Crystal Example...................................................... 193
Figure 20.1. SmaRTClock Block Diagram.............................................................. 200
Figure 20.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results.......... 208
Figure 21.1. Port I/O Functional Block Diagram ..................................................... 216
Figure 21.2. Port I/O Cell Block Diagram ............................................................... 217
Figure 21.3. Crossbar Priority Decoder with No Pins Skipped ............................... 222
Figure 21.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 223
Figure 22.1. SMBus Block Diagram ....................................................................... 238
Figure 22.2. Typical SMBus Configuration ............................................................. 239
Figure 22.3. SMBus Transaction ............................................................................ 240
Figure 22.4. Typical SMBus SCL Generation......................................................... 243
Figure 22.5. Typical Master Write Sequence ......................................................... 252
Figure 22.6. Typical Master Read Sequence ......................................................... 253
Figure 22.7. Typical Slave Write Sequence ........................................................... 254
Figure 22.8. Typical Slave Read Sequence ........................................................... 255
Figure 23.1. UART0 Block Diagram ....................................................................... 260
Figure 23.2. UART0 Baud Rate Logic .................................................................... 261
Figure 23.3. UART Interconnect Diagram .............................................................. 262
Figure 23.4. 8-Bit UART Timing Diagram............................................................... 262
Figure 23.5. 9-Bit UART Timing Diagram............................................................... 263
Figure 23.6. UART Multi-Processor Mode Interconnect Diagram .......................... 264
Figure 24.1. SPI Block Diagram ............................................................................. 268
Figure 24.2. Multiple-Master Mode Connection Diagram ....................................... 271
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Rev. 1.3