C8051F93X Datasheet, PDF (321/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 26.4. PCA0CPMn: PCA Capture/Compare Mode
Bit
7
6
5
4
3
2
1
0
Name PWM16n ECOMn CAPPn CAPNn MATn
TOGn
PWMn ECCFn
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address, Page: PCA0CPM0 = 0xDA, 0x0; PCA0CPM1 = 0xDB, 0x0; PCA0CPM2 = 0xDC, 0x0
PCA0CPM3 = 0xDD, 0x0; PCA0CPM4 = 0xDE, 0x0; PCA0CPM5 = 0xCE, 0x0
Bit Name
Function
7 PWM16n 16-bit Pulse Width Modulation Enable.
This bit enables 16-bit mode when Pulse Width Modulation mode is enabled.
0: 8 to 11-bit PWM selected.
1: 16-bit PWM selected.
6 ECOMn Comparator Function Enable.
This bit enables the comparator function for PCA module n when set to 1.
5 CAPPn Capture Positive Function Enable.
This bit enables the positive edge capture for PCA module n when set to 1.
4 CAPNn Capture Negative Function Enable.
This bit enables the negative edge capture for PCA module n when set to 1.
3 MATn Match Function Enable.
This bit enables the match function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a module's capture/compare register cause the CCFn
bit in PCA0MD register to be set to logic 1.
2 TOGn Toggle Function Enable.
This bit enables the toggle function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a module's capture/compare register cause the logic
level on the CEXn pin to toggle. If the PWMn bit is also set to logic 1, the module oper-
ates in Frequency Output Mode.
1 PWMn Pulse Width Modulation Mode Enable.
This bit enables the PWM function for PCA module n when set to 1. When enabled, a
pulse width modulated signal is output on the CEXn pin. 8 to 11-bit PWM is used if
PWM16n is cleared; 16-bit mode is used if PWM16n is set to logic 1. If the TOGn bit is
also set, the module operates in Frequency Output Mode.
0 ECCFn Capture/Compare Flag Interrupt Enable.
This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt.
0: Disable CCFn interrupts.
1: Enable a Capture/Compare Flag interrupt request when CCFn is set.
Note: When the WDTE bit is set to 1, the PCA0CPM5 register cannot be modified, and module 5 acts as the
watchdog timer. To change the contents of the PCA0CPM5 register or the function of module 5, the Watchdog
Timer must be disabled.
Rev. 1.3
321