C8051F93X Datasheet, PDF (93/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
7. Comparators
C8051F93x-C8051F92x devices include two on-chip programmable voltage comparators: Comparator 0
(CPT0) is shown in Figure 7.1; Comparator 1 (CPT1) is shown in Figure 7.2. The two comparators operate
identically, but may differ in their ability to be used as reset or wake-up sources. See the Reset Sources
chapter and the Power Management chapter for details on reset sources and low power mode wake-up
sources, respectively.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous CP0A signal is available even when the
system clock is not active. This allows the Comparator to operate and generate an output when the device
is in some low power modes.
7.1. Comparator Inputs
Each Comparator performs an analog comparison of the voltage levels at its positive (CP0+ or CP1+) and
negative (CP0- or CP1-) input. Both comparators support multiple port pin inputs multiplexed to their posi-
tive and negative comparator inputs using analog input multiplexers. The analog input multiplexers are
completely under software control and configured using SFR registers. See Section “7.6. Comparator0 and
Comparator1 Analog Multiplexers” on page 100 for details on how to select and configure Comparator
inputs.
Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be con-
figured as analog inputs and skipped by the Crossbar. See the Port I/O chapter for more details on how to
configure Port I/O pins as Analog Inputs. The Comparator may also be used to compare the logic level of
digital signals, however, Port I/O pins configured as digital inputs must be driven to a valid logic state
(HIGH or LOW) to avoid increased power consumption.
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
Analog Input Multiplexer
Px.x
VDD
CPT0MD
CP0
Interrupt
CP0
Rising-edge
CP0
Falling-edge
Px.x
Px.x
Px.x
CP0 +
CP0 -
+
-
GND
D ^SET Q
Q CLR
D ^SET Q
Q CLR
(SYNCHRONIZER)
(ASYNCHRONOUS)
Reset
Decision
Tree
Interrupt
Logic
CP0
Crossbar
CP0A
Figure 7.1. Comparator 0 Functional Block Diagram
Rev. 1.3
93