C8051F93X Datasheet, PDF (21/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
1.2. Port Input/Output
Digital and analog resources are available through 24 I/O pins (C8051F930/20) or 16 I/O pins
(C8051F931/21). Port pins are organized as three byte-wide ports. Port pins P0.0–P2.6 can be defined as
digital or analog I/O. Digital I/O pins can be assigned to one of the internal digital resources or used as
general purpose I/O (GPIO). Analog I/O pins are used by the internal analog resources. P2.7 can be used
as GPIO and is shared with the C2 Interface Data signal (C2D). See Section “27. C2 Interface” on
page 324 for more details.
The designer has complete control over which digital and analog functions are assigned to individual Port
pins, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved
through the use of a Priority Crossbar Decoder. See Section “21.3. Priority Crossbar Decoder” on
page 221 for more information on the Crossbar.
All Port I/Os are 5 V tolerant when used as digital inputs or open-drain outputs. For Port I/Os configured as
push-pull outputs, current is sourced from the VDD/DC+ supply. Port I/Os used for analog functions can
operate up to the VDD/DC+ supply voltage. See Section “21.1. Port I/O Modes of Operation” on page 217
for more information on Port I/O operating modes and the electrical specifications chapter for detailed elec-
trical specifications.
XBR0, XBR1,
XBR2, PnSKIP
Registers
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
Highest
Priority
Lowest
Priority
UART
2
SPI0
4
SPI1
2
SMBus
CP0
4
CP1
Outputs
SYSCLK
PCA
7
T0, T1
2
8
P0 _(P0.0-P0.7)
8
P1 _(P1.0-P1.7)
8
P2 _(P2.0-P2.7)
Priority
Decoder
External Interrupts
EX0 and EX1
PnMDOUT,
PnMDIN Registers
Digital
Crossbar
8
8
P0
I/O
Cells
P1
I/O
Cells
8
P2
I/O
Cell
To EMIF
To Analog Peripherals
(ADC0, CP0, and CP1 inputs,
VREF, IREF0, AGND)
P0.0
P0.7
P1.0
P1.6
P1.7
P2.0
P2.6
P2.7
P1.7–2.6 only available
on 32-pin devices
P2.7 is available on all
devices
Figure 1.5. Port I/O Functional Block Diagram
Rev. 1.3
21