C8051F93X Datasheet, PDF (307/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
26.2. PCA0 Interrupt Sources
Figure 26.3 shows a diagram of the PCA interrupt tree. There are eight independent event flags that can
be used to generate a PCA0 interrupt. They are: the main PCA counter overflow flag (CF), which is set
upon a 16-bit overflow of the PCA0 counter, an intermediate overflow flag (COVF), which can be set on an
overflow from the 8th, 9th, 10th, or 11th bit of the PCA0 counter, and the individual flags for each PCA
channel (CCF0, CCF1, CCF2, CCF3, CCF4, and CCF5), which are set according to the operation mode of
that module. These event flags are always set when the trigger condition occurs. Each of these flags can
be individually selected to generate a PCA0 interrupt, using the corresponding interrupt enable flag (ECF
for CF, ECOV for COVF, and ECCFn for each CCFn). PCA0 interrupts must be globally enabled before any
individual interrupt sources are recognized by the processor. PCA0 interrupts are globally enabled by
setting the EA bit and the EPCA0 bit to logic 1.
(for n = 0 to 5)
PCA0CPMn
P ECCMT P E
WCAA AOWC
MOP P TGMC
1 MPN n n n F
6nnn
n
n
PCA Counter/Timer 8, 9,
10 or 11-bit Overflow
PCA Counter/Timer 16-
bit Overflow
PCA Module 0
(CCF0)
PCA0CN
CCCCCCCC
FRCCCCCC
FFFFFF
543210
PCA0MD
C WW C C C E
I DD PPPC
DT L SSSF
LEC 2 1 0
K
ECCF0
0
1
0
1
PCA Module 1
(CCF1)
ECCF1
0
1
PCA Module 2
(CCF2)
ECCF2
0
1
PCA Module 3
(CCF3)
ECCF3
0
1
PCA Module 4
(CCF4)
ECCF4
0
1
PCA Module 5
(CCF5)
ECCF5
0
1
PCA0PWM
A CE
CC
ROC
LL
S VO
SS
EFV
EE
L
LL
10
Set 8, 9, 10, or 11 bit Operation
0
1
EPCA0
EA
0
1
0 Interrupt
Priority
1
Decoder
Figure 26.3. PCA Interrupt Block Diagram
Rev. 1.3
307