C8051F93X Datasheet, PDF (5/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
13.1.3.Flash Write Procedure ........................................................................... 149
13.2.Non-volatile Data Storage .............................................................................. 150
13.3.Security Options ............................................................................................. 150
13.4.Determining the Device Part Number at Run Time ........................................ 152
13.5.Flash Write and Erase Guidelines .................................................................. 153
13.5.1.VDD Maintenance and the VDD Monitor ............................................... 153
13.5.2.PSWE Maintenance ............................................................................... 154
13.5.3.System Clock ......................................................................................... 154
13.6.Minimizing Flash Read Current ...................................................................... 155
14. Power Management.............................................................................................. 159
14.1.Normal Mode .................................................................................................. 160
14.2.Idle Mode........................................................................................................ 161
14.3.Stop Mode ...................................................................................................... 161
14.4.Suspend Mode ............................................................................................... 162
14.5.Sleep Mode .................................................................................................... 162
14.6.Configuring Wakeup Sources......................................................................... 163
14.7.Determining the Event that Caused the Last Wakeup.................................... 164
14.8.Power Management Specifications ................................................................ 166
15. Cyclic Redundancy Check Unit (CRC0) ............................................................. 167
15.1.16-bit CRC Algorithm...................................................................................... 167
15.2.32-bit CRC Algorithm...................................................................................... 169
15.3.Preparing for a CRC Calculation .................................................................... 170
15.4.Performing a CRC Calculation ....................................................................... 170
15.5.Accessing the CRC0 Result ........................................................................... 170
15.6.CRC0 Bit Reverse Feature............................................................................. 174
16. On-Chip DC-DC Converter (DC0) ........................................................................ 175
16.1.Startup Behavior............................................................................................. 176
16.2.High Power Applications ............................................................................. 177
16.3.Pulse Skipping Mode...................................................................................... 177
16.4.Enabling the DC-DC Converter ...................................................................... 178
16.5.Minimizing Power Supply Noise ..................................................................... 179
16.6.Selecting the Optimum Switch Size................................................................ 179
16.7.DC-DC Converter Clocking Options ............................................................... 179
16.8.DC-DC Converter Behavior in Sleep Mode .................................................... 180
16.9.DC-DC Converter Register Descriptions ........................................................ 181
16.10.DC-DC Converter Specifications .................................................................. 182
17. Voltage Regulator (VREG0) ................................................................................. 183
17.1.Voltage Regulator Electrical Specifications .................................................... 183
18. Reset Sources....................................................................................................... 184
18.1.Power-On (VBAT Supply Monitor) Reset ....................................................... 185
18.2.Power-Fail (VDD/DC+ Supply Monitor) Reset................................................ 186
18.3.External Reset ................................................................................................ 188
18.4.Missing Clock Detector Reset ........................................................................ 188
18.5.Comparator0 Reset ........................................................................................ 188
18.6.PCA Watchdog Timer Reset .......................................................................... 188
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