C8051F93X Datasheet, PDF (282/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Table 24.1. SPI Slave Timing Parameters
Parameter
Description
Min
Max
Units
Master Mode Timing^* (See Figure 24.8 and Figure 24.9)
T_MCKH
SCK High Time
1 x T_SYSCLK
—
ns
T_MCKL
SCK Low Time
1 x T_SYSCLK
—
ns
T_MIS
MISO Valid to SCK Shift Edge
1 x T_SYSCLK + 20
—
ns
T_MIH
SCK Shift Edge to MISO Change
0
Slave Mode Timing^* (See Figure 24.10 and Figure 24.11)
—
ns
T_SE
NSS Falling to First SCK Edge
2 x T_SYSCLK
—
ns
T_SD
Last SCK Edge to NSS Rising
2 x T_SYSCLK
—
ns
T_SEZ
NSS Falling to MISO Valid
—
4 x T_SYSCLK ns
T_SDZ
NSS Rising to MISO High-Z
—
4 x T_SYSCLK ns
T_CKH
SCK High Time
5 x T_SYSCLK
—
ns
T_CKL
SCK Low Time
5 x T_SYSCLK
—
ns
T_SIS
MOSI Valid to SCK Sample Edge
2 x T_SYSCLK
—
ns
T_SIH
SCK Sample Edge to MOSI Change
2 x T_SYSCLK
—
ns
T_SOH
T_SLH
SCK Shift Edge to MISO Change
Last SCK Edge to MISO Change 
(CKPHA = 1 ONLY)
—
6 x T_SYSCLK
4 x T_SYSCLK ns
8 x T_SYSCLK ns
*Note: T_SYSCLK is equal to one period of the device system clock (SYSCLK).
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