C8051F93X Datasheet, PDF (277/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 24.2. SPInCN: SPI Control
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
SPIFn
R/W
0
WCOLn MODFn
R/W
R/W
0
0
RXOVRNn NSSnMD1 NSSnMD0
R/W
R/W
R/W
0
0
1
TXBMTn
R
1
SPInEN
R/W
0
SFR Addresses: SPI0CN = 0xF8, Bit-Addressable; SPI1CN = 0xB0, Bit-Addressable
SFR Pages: SPI0CN = 0x0, SPI1CN = 0x0
Bit
Name
Function
7
SPIFn
SPIn Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are
enabled, setting this bit causes the CPU to vector to the SPIn interrupt service
routine. This bit is not automatically cleared by hardware. It must be cleared by
software.
6
WCOLn Write Collision Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) to indicate a
write to the SPI0 data register was attempted while a data transfer was in progress.
It must be cleared by software.
5
MODFn Mode Fault Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when a mas-
ter mode collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01).
This bit is not automatically cleared by hardware. It must be cleared by software.
4 RXOVRNn Receive Overrun Flag (valid in slave mode only).
This bit is set to logic 1 by hardware (and generates a SPIn interrupt) when the
receive buffer still holds unread data from a previous transfer and the last bit of the
current transfer is shifted into the SPI shift register. This bit is not automatically
cleared by hardware. It must be cleared by software.
3:2 NSSnMD[1:0] Slave Select Mode.
Selects between the following NSS operation modes:
(See Section 24.2 and Section 24.3).
00: 3-Wire Slave or 3-Wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the
device and will assume the value of NSSMD0.
1
TXBMTn Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer.
When data in the transmit buffer is transferred to the SPI shift register, this bit will
be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer.
0
SPInEN SPIn Enable.
0: SPIn disabled.
1: SPIn enabled.
Rev. 1.3
277