C8051F93X Datasheet, PDF (82/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte
Bit
7
6
5
4
3
2
1
0
Name
AD0LT[15:8]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xC6
Bit
Name
Function
7:0 AD0LT[15:8] ADC0 Less-Than High Byte.
Most Significant Byte of the 16-bit Less-Than window compare register.
SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte
Bit
7
6
5
4
3
2
1
0
Name
AD0LT[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xC5
Bit
Name
Function
7:0 AD0LT[7:0] ADC0 Less-Than Low Byte.
Least Significant Byte of the 16-bit Less-Than window compare register.
Note: In 8-bit mode, this register should be set to 0x00.
82
Rev. 1.3