C8051F93X Datasheet, PDF (12/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
List of Tables
Table 2.1. Product Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 3.1. Pin Definitions for the C8051F92x-C8051F93x . . . . . . . . . . . . . . . . . . . 27
Table 3.2. QFN-32 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 3.3. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 3.4. QFN-24 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 3.5. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 3.6. LQFP-32 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 3.7. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 4.1.Absolute Maximum Ratings ..................................................................... 45
Table 4.2.Global Electrical Characteristics .............................................................. 46
Table 4.3.Port I/O DC Electrical Characteristics ...................................................... 54
Table 4.4.Reset Electrical Characteristics ............................................................... 59
Table 4.5.Power Management Electrical Specifications .......................................... 60
Table 4.6.Flash Electrical Characteristics ............................................................... 60
Table 4.7.Internal Precision Oscillator Electrical Characteristics ............................ 60
Table 4.8.Internal Low-Power Oscillator Electrical Characteristics ......................... 60
Table 4.9.ADC0 Electrical Characteristics ............................................................... 61
Table 4.10.Temperature Sensor Electrical Characteristics ..................................... 62
Table 4.11.Voltage Reference Electrical Characteristics ........................................ 62
Table 4.12.IREF0 Electrical Characteristics ............................................................ 63
Table 4.13.Comparator Electrical Characteristics ................................................... 64
Table 4.14.DC-DC Converter (DC0) Electrical Characteristics ............................... 66
Table 4.15.VREG0 Electrical Characteristics .......................................................... 66
Table 8.1. CIP-51 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 10.1.AC Parameters for External Memory Interface .................................... 128
Table 11.1. Special Function Register (SFR) Memory Map (Page 0x0) . . . . . . . . 129
Table 11.2. Special Function Register (SFR) Memory Map (Page 0xF) . . . . . . . . 130
Table 11.3. Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 12.1. Interrupt Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 13.1. Flash Security Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 14.1. Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 15.1. Example 16-bit CRC Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 15.2.Example 32-bit CRC Outputs .............................................................. 170
Table 16.1. IPeak Inductor Current Limit Settings . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 19.1. Recommended XFCN Settings for Crystal Mode . . . . . . . . . . . . . . . . 193
Table 19.2. Recommended XFCN Settings for RC and C modes . . . . . . . . . . . . . 194
Table 20.1.SmaRTClock Internal Registers .......................................................... 201
Table 20.2. SmaRTClock Load Capacitance Settings . . . . . . . . . . . . . . . . . . . . . 207
Table 20.3. SmaRTClock Bias Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 21.1. Port I/O Assignment for Analog Functions . . . . . . . . . . . . . . . . . . . . . 218
Table 21.2. Port I/O Assignment for Digital Functions . . . . . . . . . . . . . . . . . . . . . . 220
Table 21.3. Port I/O Assignment for External Digital Event Capture Functions . . 220
Table 22.1. SMBus Clock Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
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