C8051F93X Datasheet, PDF (43/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Figure 3.11. LQFP-32 Package Diagram
Table 3.6. LQFP-32 Package Dimensions
Dimension Min
Typ
Max
Dimension Min
Typ
Max
A
—
—
1.60
E
9.00 BSC
A1
0.05
—
0.15
E1
7.00 BSC
A2
1.35
1.40
1.45
L
0.45
0.60
0.75
b
0.30
0.37
0.45
aaa
0.20
c
0.09
—
0.20
bbb
0.20
D
9.00 BSC.
ccc
0.10
D1
7.00 BSC
ddd
0.20
e
0.80 BSC

0º
3.5º
7º
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MS-026, variation BBA.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.3
43