C8051F93X Datasheet, PDF (29/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Table 3.1. Pin Definitions for the C8051F92x-C8051F93x (Continued)
Name
P1.0
Pin Numbers
Type Description
‘F920/30 ‘F921/31
24
16 D I/O or Port 1.0. See Port I/O Section for a complete description.
A In May also be used as SCK for SPI1.
AD0*
P1.1
D I/O Address/Data 0.
23
15 D I/O or Port 1.1. See Port I/O Section for a complete description.
A In May also be used as MISO for SPI1.
AD1*
P1.2
D I/O Address/Data 1.
22
14 D I/O or Port 1.2. See Port I/O Section for a complete description.
A In May also be used as MOSI for SPI1.
AD2*
P1.3
D I/O Address/Data 2.
21
13 D I/O or Port 1.3. See Port I/O Section for a complete description.
A In May also be used as NSS for SPI1.
AD3*
P1.4
D I/O Address/Data 3.
20
12 D I/O or Port 1.4. See Port I/O Section for a complete description.
A In
AD4*
P1.5
D I/O Address/Data 4.
19
11 D I/O or Port 1.5. See Port I/O Section for a complete description.
A In
AD5*
P1.6
D I/O
Address/Data 5.
18
10 D I/O or Port 1.6. See Port I/O Section for a complete description.
A In
AD6*
P1.7*
17
D I/O Address/Data 6.
D I/O or Port 1.7. See Port I/O Section for a complete description.
A In
AD7*
P2.0*
16
D I/O Address/Data 7.
D I/O or Port 2.0. See Port I/O Section for a complete description.
A In
AD8*
D I/O Address/Data 8.
*Note: Available only on the C8051F920/30.
Rev. 1.3
29