C8051F93X Datasheet, PDF (71/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
5.2.3. Burst Mode
Burst Mode is a power saving feature that allows ADC0 to remain in a low power state between conver-
sions. When Burst Mode is enabled, ADC0 wakes from a low power state, accumulates 1, 4, 8, 16, 32, or
64 using an internal burst mode clock (approximately 25 MHz), then re-enters a low power state. Since the
burst mode clock is independent of the system clock, ADC0 can perform multiple conversions then enter a
low power state within a single system clock cycle, even if the system clock is slow (e.g., 32.768 kHz), or
suspended.
Burst Mode is enabled by setting BURSTEN to logic 1. When in burst mode, AD0EN controls the ADC0
idle power state (i.e. the state ADC0 enters when not tracking or performing conversions). If AD0EN is set
to logic 0, ADC0 is powered down after each burst. If AD0EN is set to logic 1, ADC0 remains enabled after
each burst. On each convert start signal, ADC0 is awakened from its Idle Power State. If ADC0 is powered
down, it will automatically power up and wait the programmable Power-Up Time controlled by the
AD0PWR bits. Otherwise, ADC0 will start tracking and converting immediately. Figure 5.3 shows an exam-
ple of Burst Mode Operation with a slow system clock and a repeat count of 4.
When burst mode is enabled, a single convert start will initiate a number of conversions equal to the repeat
count. When burst mode is disabled, a convert start is required to initiate each conversion. In both modes,
the ADC0 End of Conversion Interrupt Flag (AD0INT) will be set after “repeat count” conversions have
been accumulated. Similarly, the Window Comparator will not compare the result to the greater-than and
less-than registers until “repeat count” conversions have been accumulated.
In Burst Mode, tracking is determined by the settings in AD0PWR and AD0TK. The default settings for
these registers will work in most applications without modification; however, settling time requirements may
need adjustment in some applications. Refer to “5.2.4. Settling Time Requirements” on page 73 for more
details.
Notes:
• Setting AD0TM to 1 will insert an additional 3 SAR clocks of tracking before each conversion, regardless of the
settings of AD0PWR and AD0TK.
• When using Burst Mode, care must be taken to issue a convert start signal no faster than once every four SYS-
CLK periods. This includes external convert start signals.
• A rising edge of external start-of-conversion (CNVSTR) will cause only one ADC conversion in Burst
Mode, regardless of the value of the Repeat Count field. The end-of-conversion interrupt will occur
after the number of conversions specified in Repeat Count have completed. In other words, if Repeat
Count is set to 4, four pulses on CNVSTR will cause an ADC end-of-conversion interrupt. Refer to the
bottom portion of Figure 5.3, “Burst Mode Tracking Example with Repeat Count Set to 4,” on page 72
for an example.
• To start multiple conversions in Burst Mode with one external start-of-conversion signal, the external
interrupts (/INT0 or /INT1) or Port Match can be used to trigger an ISR that writes to AD0BUSY. Exter-
nal interrupts are configurable to be active low or active high, edge or level sensitive, but is only avail-
able on a limited number of pins. Port Match is only level sensitive, but is available on more port pins
than the external interrupts. Refer to Section “12.6. External Interrupts INT0 and INT1” on
page 146 for details on external interrupts and Section “21.4. Port Match” on page 227 for details on
Port Match.
Rev. 1.3
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