C8051F93X Datasheet, PDF (225/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 21.2. XBR1: Port I/O Crossbar Register 1
Bit
7
6
5
4
3
2
1
0
Name
SPI1E
T1E
T0E
ECIE
PCA0ME[2:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xE2
Bit Name
Function
7
Unused Unused.
Read = 0b; Write = Don’t Care.
6
SPI1E SPI1 I/O Enable.
0: SPI0 I/O unavailable at Port pin.
1: SCK (for SPI1) routed to P1.0.
MISO (for SPI1) routed to P1.1.
MOSI (for SPI1) routed to P1.2.
NSS (for SPI1) routed to P1.3 only if SPI1 is configured to 4-wire mode.
5
T1E Timer1 Input Enable.
0: T1 input unavailable at Port pin.
1: T1 input routed to Port pin.
4
T0E Timer0 Input Enable.
0: T0 input unavailable at Port pin.
1: T0 input routed to Port pin.
3
ECIE PCA0 External Counter Input (ECI) Enable.
0: PCA0 external counter input unavailable at Port pin.
1: PCA0 external counter input routed to Port pin.
2:0 PCA0ME PCA0 Module I/O Enable.
000: All PCA0 I/O unavailable at Port pin.
001: CEX0 routed to Port pin.
010: CEX0, CEX1 routed to Port pins.
011: CEX0, CEX1, CEX2 routed to Port pins.
100: CEX0, CEX1, CEX2 CEX3 routed to Port pins.
101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to Port pins.
110: CEX0, CEX1, CEX2, CEX3, CEX4, CEX5 routed to Port pins.
111: Reserved.
Note: SPI1 can be assigned either 3 or 4 Port I/O pins.
Rev. 1.3
225