C8051F93X Datasheet, PDF (173/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 15.4. CRC0AUTO: CRC0 Automatic Control
Bit
7
6
5
4
3
2
1
0
Name AUTOEN CRCDONE
CRC0ST[5:0]
Type
R/W
R/W
Reset
0
1
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0x96
Bit
Name
Function
7
AUTOEN Automatic CRC Calculation Enable.
When AUTOEN is set to 1, any write to CRC0CN will initiate an automatic CRC
starting at Flash sector CRC0ST and continuing for CRC0CNT sectors.
6 CRCDONE CRCDONE Automatic CRC Calculation Complete.
Set to 0 when a CRC calculation is in progress. Note that code execution is
stopped during a CRC calculation, therefore reads from firmware will always
return 1.
5:0 CRC0ST[5:0] Automatic CRC Calculation Starting Flash Sector.
These bits specify the Flash sector to start the automatic CRC calculation. The
starting address of the first Flash sector included in the automatic CRC calculation
is CRC0ST x 1024.
SFR Definition 15.5. CRC0CNT: CRC0 Automatic Flash Sector Count
Bit
7
6
5
4
3
2
1
0
Name
CRC0CNT[5:0]
Type
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0x97
Bit
Name
7:6
Unused Unused.
Read = 00b; Write = Don’t Care.
Function
5:0 CRC0CNT[5:0] Automatic CRC Calculation Flash Sector Count.
These bits specify the number of Flash sectors to include in an automatic CRC
calculation. The starting address of the last Flash sector included in the automatic
CRC calculation is (CRC0ST+CRC0CNT) x 1024.
Rev. 1.3
173