C8051F93X Datasheet, PDF (23/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
1.5. 10-Bit SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous
Low Power Burst Mode
C8051F93x-C8051F92x devices have a 300 ksps, 10-bit successive-approximation-register (SAR) ADC
with integrated track-and-hold and programmable window detector. ADC0 also has an autonomous low
power Burst Mode which can automatically enable ADC0, capture and accumulate samples, then place
ADC0 in a low power shutdown mode without CPU intervention. It also has a 16-bit accumulator that can
automatically average the ADC results, providing an effective 11, 12, or 13 bit ADC result without any addi-
tional CPU intervention.
The ADC can sample the voltage at any of the GPIO pins (with the exception of P2.7) and has an on-chip
attenuator that allows it to measure voltages up to twice the voltage reference. Additional ADC inputs
include an on-chip temperature sensor, the VDD/DC+ supply voltage, the VBAT supply voltage, and the
internal digital supply voltage.
ADC0CN
ADC0TK
ADC0PWR
Burst Mode Logic
From
AMUX0
AIN+
VDD
10-Bit
SAR
ADC
000
Start
Conversion
001
010
011
100
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 3 Overflow
CNVSTR Input
16-Bit Accumulator
ADC0LTH ADC0LTL
A D 0W IN T
Window
Compare
32
Logic
ADC0CF
ADC0GTH ADC0GTL
Figure 1.7. ADC0 Functional Block Diagram
Rev. 1.3
23