C8051F93X Datasheet, PDF (326/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
C2 Register Definition 27.4. FPCTL: C2 Flash Programming Control
Bit
7
6
5
4
3
2
1
0
Name
FPCTL[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
C2 Address: 0x02
Bit Name
Function
7:0 FPCTL[7:0] Flash Programming Control Register.
This register is used to enable Flash programming via the C2 interface. To enable C2
Flash programming, the following codes must be written in order: 0x02, 0x01. Note
that once C2 Flash programming is enabled, a system reset must be issued to
resume normal operation.
C2 Register Definition 27.5. FPDAT: C2 Flash Programming Data
Bit
7
6
5
4
3
2
1
0
Name
FPDAT[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
C2 Address: 0xB4
Bit Name
Function
7:0 FPDAT[7:0] C2 Flash Programming Data Register.
This register is used to pass Flash commands, addresses, and data during C2 Flash
accesses. Valid commands are listed below.
Code
0x06
0x07
0x08
0x03
Command
Flash Block Read
Flash Block Write
Flash Page Erase
Device Erase
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Rev. 1.3