C8051F93X Datasheet, PDF (135/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Table 11.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address SFR Page
Description
TMOD
0x89
0x0 Timer/Counter Mode
TMR2CN
0xC8
0x0 Timer/Counter 2 Control
TMR2H
0xCD
0x0 Timer/Counter 2 High
TMR2L
0xCC
0x0 Timer/Counter 2 Low
TMR2RLH
0xCB
0x0 Timer/Counter 2 Reload High
TMR2RLL
0xCA
0x0 Timer/Counter 2 Reload Low
TMR3CN
0x91
0x0 Timer/Counter 3 Control
TMR3H
0x95
0x0 Timer/Counter 3 High
TMR3L
0x94
0x0 Timer/Counter 3 Low
TMR3RLH
0x93
0x0 Timer/Counter 3 Reload High
TMR3RLL
0x92
0x0 Timer/Counter 3 Reload Low
TOFFH
0x86
0xF Temperature Offset High
TOFFL
0x85
0xF Temperature Offset Low
VDM0CN
0xFF
0x0 VDD Monitor Control
XBR0
0xE1
0x0 Port I/O Crossbar Control 0
XBR1
0xE2
0x0 Port I/O Crossbar Control 1
XBR2
0xE3
0x0 Port I/O Crossbar Control 2
Page
290
296
298
298
297
297
302
304
304
303
303
88
88
187
224
225
226
Rev. 1.3
135