C8051F93X Datasheet, PDF (109/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
8.2. CIP-51 Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic l. Future product versions may use these bits to implement new features in which
case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of
the remaining SFRs are included in the sections of the data sheet associated with their corresponding sys-
tem function.
SFR Definition 8.1. DPL: Data Pointer Low Byte
Bit
7
6
5
4
3
2
1
0
Name
DPL[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = All Pages; SFR Address = 0x82
Bit Name
Function
7:0 DPL[7:0] Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indi-
rectly addressed Flash memory or XRAM.
SFR Definition 8.2. DPH: Data Pointer High Byte
Bit
7
6
5
4
3
2
1
0
Name
DPH[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = All Pages; SFR Address = 0x83
Bit Name
Function
7:0 DPH[7:0] Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indi-
rectly addressed Flash memory or XRAM.
Rev. 1.3
109