C8051F93X Datasheet, PDF (84/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
5.5. ADC0 Analog Multiplexer
ADC0 on C8051F93x-C8051F92x has an analog multiplexer, referred to as AMUX0.
AMUX0 selects the positive inputs to the single-ended ADC0. Any of the following may be selected as the
positive input: Port I/O pins, the on-chip temperature sensor, the VBAT Power Supply, Regulated Digital
Supply Voltage (Output of VREG0), VDD/DC+ Supply, or the positive input may be connected to GND. The
ADC0 input channels are selected in the ADC0MX register described in SFR Definition 5.12.
ADC0MX
P0.0
P2.6*
Temp
Sensor
VBAT
Digital Supply
VDD/DC+
AMUX
Programmable
Attenuator
AIN+ _ADC0
Gain = 0.5 or 1
*P1.7-P2.6 only available as
inputs on 32-pin packages
Figure 5.7. ADC0 Multiplexer Block Diagram
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be
configured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for
analog input, set to 0 the corresponding bit in register PnMDIN and disable the digital driver (PnMDOUT =
0 and Port Latch = 1). To force the Crossbar to skip a Port pin, set to 1 the corresponding bit in register
PnSKIP. See Section “21. Port Input/Output” on page 216 for more Port I/O configuration details.
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Rev. 1.3