C8051F93X Datasheet, PDF(118/330 Page) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

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C8051F93X Datasheet, PDF (118/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

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C8051F93x-C8051F92x

10.4. Multiplexed External Memory Interface

For a Multiplexed external memory interface, the Data Bus and the lower 8-bits of the Address Bus share

the same Port pins: AD[7:0]. For most devices with an 8-bit interface, the upper address bits are not used

and can be used as GPIO if the external memory interface is used in 8-bit non-banked mode. If the

external memory interface is used in 8-bit banked mode, or 16-bit mode, then the address pins will be

driven with the upper 4 address bits and cannot be used as GPIO.

GPIO (4-bit)

LEDs/Switches

E A[11:8]

M

I

AD[7:0]

ADDRESS BUS (12-bit or 8-bit)

VDD

(Optional)

8

DATA BUS

Ethernet

Controller

(8-bit Interface)

AD[7:0]

F WR

CS

WR

RD

RD

ALE

ALE

Figure 10.1. Multiplexed Configuration Example

Many devices with a slave parallel memory interface, such as SRAM chips, only support a non-multiplexed

memory bus. When interfacing to such a device, an external latch (74HC373 or equivalent logic gate) can

be used to hold the lower 8-bits of the RAM address during the second half of the memory cycle when the

address/data bus contains data. The external latch, controlled by the ALE (Address Latch Enable) signal,

is automatically driven by the External Memory Interface logic. An example SRAM interface showing

multiplexed to non-multiplexed conversion is shown in Figure 10.2.

This example is showing that the external MOVX operation can be broken into two phases delineated by

the state of the ALE signal. During the first phase, ALE is high and the lower 8-bits of the Address Bus are

presented to AD[7:0]. During this phase, the address latch is configured such that the Q outputs reflect the

states of the D inputs. When ALE falls, signaling the beginning of the second phase, the address latch

outputs remain fixed and are no longer dependent on the latch inputs. Later in the second phase, the Data

Bus controls the state of the AD[7:0] port at the time RD or WR is asserted.

See Section â10.6. External Memory Interface Timingâ on page 121 for detailed timing diagrams.

118

Rev. 1.3

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