C8051F93X Datasheet, PDF (247/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 22.2. SMB0CN: SMBus Control
Bit
7
6
5
4
3
2
1
0
Name ^{MASTER TXMODE STA}
STO
ACKRQ ARBLOST ACK
SI
Type
R
R
R/W
R/W
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xC0; Bit-Addressable
Bit Name
Description
Read
Write
7 MASTER SMBus Master/Slave
0: SMBus operating in
N/A
Indicator. This read-only bit slave mode.
indicates when the SMBus is 1: SMBus operating in
operating as a master.
master mode.
6 TXMODE SMBus Transmit Mode
0: SMBus in Receiver
N/A
Indicator. This read-only bit Mode.
indicates when the SMBus is 1: SMBus in Transmitter
operating as a transmitter. Mode.
5
STA SMBus Start Flag.
0: No Start or repeated
Start detected.
1: Start or repeated Start
detected.
0: No Start generated.
1: When Configured as a
Master, initiates a START
or repeated START.
4
STO SMBus Stop Flag.
0: No Stop condition
0: No STOP condition is
detected.
transmitted.
1: Stop condition detected 1: When configured as a
(if in Slave Mode) or pend- Master, causes a STOP
ing (if in Master Mode). condition to be transmit-
ted after the next ACK
cycle.
Cleared by Hardware.
3 ACKRQ SMBus Acknowledge
Request.
0: No Ack requested
N/A
1: ACK requested
2 ARBLOST SMBus Arbitration Lost
0: No arbitration error.
N/A
Indicator.
1: Arbitration Lost
1
ACK SMBus Acknowledge.
0: NACK received.
1: ACK received.
0: Send NACK
1: Send ACK
0
SI
SMBus Interrupt Flag.
0: No interrupt pending 0: Clear interrupt, and initi-
This bit is set by hardware 1: Interrupt Pending
under the conditions listed in
Table 15.3. SI must be cleared
ate next state machine
event.
1: Force interrupt.
by software. While SI is set,
SCL is held low and the
SMBus is stalled.
Rev. 1.3
247