C8051F93X Datasheet, PDF (63/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Table 4.12. IREF0 Electrical Characteristics
V_DD = 1.8 to 3.6 V, –40 to +85 °C, unless otherwise specified.
Parameter
Resolution
Conditions
Min
Static Performance
Output Compliance Range
Low Power Mode, Source
0
High Current Mode, Source
0
Low Power Mode, Sink
0.3
High Current Mode, Sink
0.8
Integral Nonlinearity
—
Differential Nonlinearity
—
Offset Error
—
Low Power Mode, Source
—
Full Scale Error
High Current Mode, Source
—
Low Power Mode, Sink
—
High Current Mode, Sink
—
Absolute Current Error
Low Power Mode
—
Sourcing 20 µA
Output Settling Time to 1/2 LSB
Dynamic Performance
—
Startup Time
—
Net Power Supply Current 
(V_DD supplied to IREF0 minus
any output source current)
Power Consumption
Low Power Mode, Source
IREF0DAT = 000001
—
IREF0DAT = 111111
—
High Current Mode, Source
IREF0DAT = 000001
—
IREF0DAT = 111111
—
Low Power Mode, Sink
IREF0DAT = 000001
—
IREF0DAT = 111111
—
High Current Mode, Sink
IREF0DAT = 000001
—
IREF0DAT = 111111
—
Typ
Max
Units
6
bits
—
—
—
—
<±0.2
V_DD – 0.4
V_DD – 0.8
V_DD
V_DD
±1.0
V
LSB
<±0.2 ±1.0
LSB
<±0.1 ±0.5
LSB
—
±5
%
—
±6
%
—
±8
%
—
±8
%
<±1
±3
%
300
—
ns
1
—
µs
10
—
µA
10
—
µA
10
—
µA
10
—
µA
1
—
µA
11
—
µA
12
—
µA
81
—
µA
Rev. 1.3
63