C8051F93X Datasheet, PDF (155/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
13.6. Minimizing Flash Read Current
The Flash memory in the C8051F93x-C8051F92x devices is responsible for a substantial portion of the
total digital supply current when the device is executing code. Below are suggestions to minimize Flash
read current.
1. Use idle, suspend, or sleep modes while waiting for an interrupt, rather than polling the inter-
rupt flag. Idle mode is particularly well-suited for use in implementing short pauses, since the
wake-up time is no more than three system clock cycles. See the Power Management chapter
for details on the various low-power operating modes.
2. C8051F93x-C8051F92x devices have a one-shot timer that saves power when operating at
system clock frequencies of 10 MHz or less. The one-shot timer generates a minimum-dura-
tion enable signal for the Flash sense amps on each clock cycle in which the Flash memory is
accessed. This allows the Flash to remain in a low power state for the remainder of the long
clock cycle.
At clock frequencies above 10 MHz, the system clock cycle becomes short enough that the
one-shot timer no longer provides a power benefit. Disabling the one-shot timer at higher fre-
quencies reduces power consumption. The one-shot is enabled by default, and it can be dis-
abled (bypassed) by setting the BYPASS bit (FLSCL.6) to logic 1. To re-enable the one-shot,
clear the BYPASS bit to logic 0. See the note in SFR Definition 13.3. FLSCL: Flash Scale for
more information on how to properly clear the BYPASS bit.
3. Flash read current depends on the number of address lines that toggle between sequential
Flash read operations. In most cases, the difference in power is relatively small (on the order
of 5%).
The Flash memory is organized in rows. Each row in the C8051F9xx Flash contains 128
bytes. A substantial current increase can be detected when the read address jumps from one
row in the Flash memory to another. Consider a 3-cycle loop (e.g., SJMP $, or while(1);) which
straddles a 128-byte Flash row boundary. The Flash address jumps from one row to another
on two of every three clock cycles. This can result in a current increase of up 30% when com-
pared to the same 3-cycle loop contained entirely within a single row.
To minimize the power consumption of small loops, it is best to locate them within a single row,
if possible. To check if a loop is contained within a Flash row, divide the starting address of the
first instruction in the loop by 128. If the remainder (result of modulo operation) plus the length
of the loop is less than 127, then the loop fits inside a single Flash row. Otherwise, the loop will
be straddling two adjacent Flash rows. If a loop executes in 20 or more clock cycles, then the
transitions from one row to another will occur on relatively few clock cycles, and any resulting
increase in operating current will be negligible.
Note: Future 16 and 8 kB derivatives in this product family will use a Flash memory that is organized in rows of 64
bytes each. To maintain code compatibility across the entire family, it is best to locate small loops within a single
64-byte segment.
Rev. 1.3
155