C8051F93X Datasheet, PDF (73/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
5.2.4. Settling Time Requirements
A minimum amount of tracking time is required before each conversion can be performed, to allow the
sampling capacitor voltage to settle. This tracking time is determined by the AMUX0 resistance, the ADC0
sampling capacitance, any external source resistance, and the accuracy required for the conversion. Note
that in low-power tracking mode, three SAR clocks are used for tracking at the start of every conversion.
For many applications, these three SAR clocks will meet the minimum tracking time requirements, and
higher values for the external source impedance will increase the required tracking time.
Figure 5.4 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling
accuracy (SA) may be approximated by Equation 5.1. When measuring the Temperature Sensor output or
V_DD with respect to GND, R_TOTAL reduces to R_MUX. See Table 4.9 for ADC0 minimum settling time require-
ments as well as the mux impedance and sampling capacitor values.
t
=
ln


S^-2---A^{-n-}

R_TOTALC_SAMPLE
Equation 5.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R_TOTAL is the sum of the AMUX0 resistance and any external source resistance.
n is the ADC resolution in bits (10).
MUX Select
P0.x
R_MUX
RC_Input= R_MUX * C_SAMPLE
C_SAMPLE
Note: The value of CSAMPLE depends on the PGA Gain. See Table 4.9 for details.
Figure 5.4. ADC0 Equivalent Input Circuits
Rev. 1.3
73