C8051F93X Datasheet, PDF (123/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 10.2. EMI0CF: External Memory Configuration
Bit
7
6
5
4
3
2
1
0
Name
EMD[1:0]
EALE[1:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
1
1
SFR Page = 0x0; SFR Address = 0xAB
Bit
Name
Function
7:4 Unused Unused.
Read = 0000b. Write = Don’t Care.
3:2
EMD EMIF Operating Mode Select.
Selects the operating mode of the External Memory Interface. See Section
“10.5. External Memory Interface Operating Modes” on page 120.
00: Internal Only.
01: Split Mode without Bank Select.
10: Split Mode with Bank Select.
11: External Only.
1:0
EALE ALE Pulse Width Select Bits.
Selects the ALE pulse width.
00: ALE high and ALE low pulse width = 1 SYSCLK cycle.
01: ALE high and ALE low pulse width = 2 SYSCLK cycles.
10: ALE high and ALE low pulse width = 3 SYSCLK cycles.
11: ALE high and ALE low pulse width = 4 SYSCLK cycles.
Rev. 1.3
123